1. Technical Field
This disclosure relates to a current-mode control type DC-DC (direct current to direct current) converter used for power supplies in electronic devices, and a control method for a current-mode control type DC-DC converter.
2. Discussion of the Background
Currently, as power supply circuits used in portable electronic devices, non-insulated DC-DC converters that include inductors capable of downsizing and obtaining higher efficiency are widely used.
Classified by feedback method, there are two types of DC-DC converters, those employing a voltage-mode control method and those employing a current-mode control method.
The current-mode control type DC-DC converters have a number of advantages. For example, a line regulation expressed as a percentage of change in output voltage relative to the change in input voltage is higher, compensating signal phases as well as controlling the current are easier, and they are adapted to have a large capacity of electric power by arranging multiple current mode DC-DC converters in parallel. Therefore, at present, current-mode control type DC-DC converters are widely used.
FIG. 3 illustrates a configuration of a known DC-DC converter 100. The DC-DC converter 100 includes a slope voltage generation circuit 115, a fixed slope compensation voltage generation circuit 116, an amended slope compensation voltage generation circuit 117, a reference voltage generation unit 121, an error amplifier circuit 110, a PWM (pulse width modulation) control comparator 111, a RS (Reset-Set) flip-flop circuit 112, a driver circuit 113, a switching transistor M101, a synchronous rectification transistor M102, PMOS (P-channel metal oxide semiconductor) transistors M103 and M104, an inductor L101, a capacitor C101, and resistors R101 through R103. The DC-DC converter 100 further includes a power input terminal Vin, ground terminals Vss, an output terminal Vout, and an external-control bias PABIAS.
The slope voltage generation circuit 115 includes operational amplifier circuits 118 and 119, PMOS transistors M105, M106 and M107, NMOS (N-channel metal oxide semiconductor) transistor M108, and resistors R104 through R108. The PMOS transistors M106 and M107 form a current mirror circuit.
The fixed slope compensation voltage generation circuit 116 includes an electric current source L101, a PMOS transistor M109, a NMOS transistor M110, a capacitor C102, and a resistor R109.
The amended slope compensation voltage generation circuit 117 includes an operational amplifier circuit 120, PMOS transistors M113 and M114, NMOS transistors M111, M112, and M115, and a resistor R110. The PMOS transistors M113 and M114 form one current mirror circuit, and the NMOS transistors M111 and M112 form another current mirror circuit.
With reference to a timing chart shown in FIG. 4, operation of the known DC-DC converter 100 is described below.
A clock signal is inputted to a set terminal S of the RS flip-flop circuit 112, and the RS flip-flop circuit 112 is set up at every clock signal period. When the RS flip-flop circuit 112 is set up, an output signal of an output terminal Q thereof becomes high, and the signal is applied to an input terminal I of the driver circuit 113. Then, the driver circuit 113 turns both a control signal PHS outputted from an output terminal P and a control signal NLS outputted from an output terminal N low. Therefore, the switching transistor M101 is turned on, and the synchronous rectification transistor M102 is turned off. At this time, the PMOS transistors M103 and M104 forming a series circuit 114 connected in parallel to the switching transistor M101 are turned on.
Subsequently, when the switching transistor M101 is turned on, an electric current IL is supplied from a power input terminal Vin to the inductor L101. At this time, a voltage drop that is proportional to the inductor current IL is generated across a source and a drain of the switching transistor M101. The voltage drop is divided by the PMOS transistors M103 and M104, and the divided voltage is picked up as a voltage between a source and a drain of the PMOS transistor M103. This voltage is a voltage Vsense.
The voltage Vsense is supplied to a non-inverting input terminal of the operational amplifier circuit 118. An inverting output terminal of the operational amplifier circuit 118 is connected to a source of the PMOS transistor M105, and an output terminal thereof is connected to a gate of the PMOS transistor M105. The resistor R106 is connected between the source of the transistor M105 and the power input terminal Vin. The resistor R108 is connected between a drain of the transistor M105 and the ground terminal Vss.
Therefore, a drain voltage VA of the PMOS transistor M105 is proportional to the voltage Vsense and is a voltage changed to a ground standard voltage. Since the inductor current IL is increased over time, the voltage VA is increased over time as shown in FIG. 4.
It is to be noted that the voltage VA starts from a voltage in excess of 0 V (Volt) because the DC-DC converter operates in a continuous mode, in which the inductor current IL flows through the synchronous rectification transistor M102 while the switching transistor M101 is off, and the inductor current IL does not decrease to 0 A (Ampere) until the switching transistor M101 is turned on next time.
Next, ignoring operation of the amended slope compensation voltage generation circuit 117, operation of the fixed slope compensation voltage generation circuit 116 is described below.
When the control signal PHS is high, the NMOS transistor M110 is on, and a capacitor C102 discharges. At this time, the PMOS transistor M109 is off, and an electric current supply from the electric current source I101 to the capacitor C102 is stopped.
As described above, when the control signal PHS becomes low by inputting the clock signal to the RS flip-flop circuit 112, the NMOS transistor M110 is tuned off, and the PMOS transistor M109 is turned on. Then, the capacitor C102 is recharged by the electric current source I101, and a voltage VB at a junction node between a drain of the PMOS transistor M109 and the capacitor C102 is linearly increased as shown in FIG. 4.
The voltage VB is added to the voltage VA via the resistors R107 and R109, thus generating a voltage VC shown in FIG. 4. The voltage VC is applied to an operating amplifier circuit 119 and to a non-inverting input terminal of the PWM comparator 111 via the current mirror circuit constituted by the PMOS transistors M107 and M106.
By contrast, an output voltage Vout of the known DC-DC converter 100 is divided by the resistors R101 and R102 and inputted to an inverting input terminal of the error amplifier circuit 110. The reference voltage Vref is applied to a non-inverting input terminal of the error amplifier circuit 110.
The error amplifier circuit 110 outputs an error voltage Verr that is an amplified difference voltage between the divided output voltage Vout and the reference voltage Vref. The error voltage Verr is applied to an inverting input terminal of the PWM comparator 111.
As the voltage VC and the error voltage Verr in shown in FIG. 4 indicate, when the voltage VC is increased over time and reaches the error voltage Verr, an output signal of the PWM comparator 111 becomes high, and the RS flip-flop circuit 112 is reset.
Then, the output signal outputted from the output terminal Q becomes low, and the driver circuit 113 receives the signal thus outputted and switches the control signals PHS and NLS to high level.
Subsequently, the switching transistor M101 is turned off, and the synchronous rectification transistor M102 is turned on. At this time, because the NMOS transistor M110 is turned on, the capacitor C102 discharges, and the voltage VB is decreased to the ground voltage.
Further, because the PMOS transistor M109 is turned off, the electric current from the electric current source I101 is interrupted. Additionally, because the PMOS transistors M103 and M104 are turned off, the voltage Vsense becomes substantially equal to the input voltage Vin, and the voltage VA is decreased to the ground voltage.
Then, when the clock signal becomes high next time and the control signal PHS becomes low, the DC-DC converter 100 repeats the above-described operation.
However, in the above-described known slope voltage generation circuit, after the transistor M101 is turned off, the voltage VC is not immediately decreased to the ground voltage but is decreased slowly as indicated by solid curved lines shown in FIG. 4.
This situation occurs because it takes time to discharge the charge contained in a stray capacitance generated in an area from the junction node C to the non-inverting input terminal of the PWM comparator 111. If the above-described time lengthens and the voltage VC is not decreased to the ground voltage until a next clock signal is inputted, the residual voltage is added to the voltage VC in the next cycle and an accurate switching period cannot be obtained. As a result, the output voltage fluctuates, which is a problem.
In view of the foregoing, there is market demand for DC-DC converters capable of reducing fluctuations in the output voltage.